JPH03101528U - - Google Patents
Info
- Publication number
- JPH03101528U JPH03101528U JP948390U JP948390U JPH03101528U JP H03101528 U JPH03101528 U JP H03101528U JP 948390 U JP948390 U JP 948390U JP 948390 U JP948390 U JP 948390U JP H03101528 U JPH03101528 U JP H03101528U
- Authority
- JP
- Japan
- Prior art keywords
- bonding position
- window hole
- semiconductor element
- tab tape
- bonded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000003566 sealing material Substances 0.000 claims description 2
Landscapes
- Wire Bonding (AREA)
Description
第1図は本考案に係る半導体装置の実施例を示
す断面図(要部拡大図を含む)、第2図は第1図
の要部の拡大平面図である。 1……タブテープ、2……配線基板、3……半
導体素子、4……導通スルーホール、7……封止
材、A……回路基板、A′……ボンデイング位置
。
す断面図(要部拡大図を含む)、第2図は第1図
の要部の拡大平面図である。 1……タブテープ、2……配線基板、3……半
導体素子、4……導通スルーホール、7……封止
材、A……回路基板、A′……ボンデイング位置
。
Claims (1)
- タブテープの半導体素子がボンデイングされる
ボンデイング位置に窓孔が開孔されてその周りに
配線基板が積層一体化され、配線基板の配線とタ
ブテープのリードとを導通スルーホールで電気的
に接続した回路基板と、前記ボンデイング位置に
ボンデイングされた半導体素子と、前記窓孔を通
じて前記ボンデイング位置の表裏両面側に充填さ
れた封止材とを備えてなる半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990009483U JP2525354Y2 (ja) | 1990-01-31 | 1990-01-31 | 半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990009483U JP2525354Y2 (ja) | 1990-01-31 | 1990-01-31 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03101528U true JPH03101528U (ja) | 1991-10-23 |
| JP2525354Y2 JP2525354Y2 (ja) | 1997-02-12 |
Family
ID=31513083
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990009483U Expired - Fee Related JP2525354Y2 (ja) | 1990-01-31 | 1990-01-31 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2525354Y2 (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6867068B2 (en) | 1996-10-17 | 2005-03-15 | Seiko Epson Corporation | Semiconductor device, method of making the same, circuit board, and film carrier tape |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03129745A (ja) * | 1989-10-16 | 1991-06-03 | Sumitomo Bakelite Co Ltd | 半導体装置の実装方法 |
-
1990
- 1990-01-31 JP JP1990009483U patent/JP2525354Y2/ja not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03129745A (ja) * | 1989-10-16 | 1991-06-03 | Sumitomo Bakelite Co Ltd | 半導体装置の実装方法 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6867068B2 (en) | 1996-10-17 | 2005-03-15 | Seiko Epson Corporation | Semiconductor device, method of making the same, circuit board, and film carrier tape |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2525354Y2 (ja) | 1997-02-12 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |