JPH0355982B2 - - Google Patents

Info

Publication number
JPH0355982B2
JPH0355982B2 JP57085201A JP8520182A JPH0355982B2 JP H0355982 B2 JPH0355982 B2 JP H0355982B2 JP 57085201 A JP57085201 A JP 57085201A JP 8520182 A JP8520182 A JP 8520182A JP H0355982 B2 JPH0355982 B2 JP H0355982B2
Authority
JP
Japan
Prior art keywords
chip
semiconductor
pad
evaluation
stress
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57085201A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58200549A (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP57085201A priority Critical patent/JPS58200549A/ja
Publication of JPS58200549A publication Critical patent/JPS58200549A/ja
Publication of JPH0355982B2 publication Critical patent/JPH0355982B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
JP57085201A 1982-05-18 1982-05-18 半導体評価用装置 Granted JPS58200549A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57085201A JPS58200549A (ja) 1982-05-18 1982-05-18 半導体評価用装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57085201A JPS58200549A (ja) 1982-05-18 1982-05-18 半導体評価用装置

Publications (2)

Publication Number Publication Date
JPS58200549A JPS58200549A (ja) 1983-11-22
JPH0355982B2 true JPH0355982B2 (cs) 1991-08-27

Family

ID=13852003

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57085201A Granted JPS58200549A (ja) 1982-05-18 1982-05-18 半導体評価用装置

Country Status (1)

Country Link
JP (1) JPS58200549A (cs)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0740581B2 (ja) * 1987-05-18 1995-05-01 富士通株式会社 半導体集積回路及び製造方法
JP5649478B2 (ja) * 2011-02-16 2015-01-07 三菱電機株式会社 半導体装置及びその試験方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5140878A (cs) * 1974-10-04 1976-04-06 Hitachi Ltd

Also Published As

Publication number Publication date
JPS58200549A (ja) 1983-11-22

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