JPS5996849U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS5996849U
JPS5996849U JP1982192202U JP19220282U JPS5996849U JP S5996849 U JPS5996849 U JP S5996849U JP 1982192202 U JP1982192202 U JP 1982192202U JP 19220282 U JP19220282 U JP 19220282U JP S5996849 U JPS5996849 U JP S5996849U
Authority
JP
Japan
Prior art keywords
metal
semiconductor equipment
reaction layer
gold
tin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1982192202U
Other languages
English (en)
Inventor
角和　晴夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP1982192202U priority Critical patent/JPS5996849U/ja
Publication of JPS5996849U publication Critical patent/JPS5996849U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H10W72/9226—Bond pads being integral with underlying chip-level interconnections with via interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は従来のダイオードチップの断面図、第２図は従
来のタイオードのパッケージへの組立図、第３図及び第
４図は何れもこの考案の半導体装置の生成品断面図、第
５図はこの考案ダイオードチップの断面図である。 各図で、１・・・金属、２・・・モリブテン層、３・・
・チタン層、４・・・酸化膜、１２・・・錫層、１３・
・・金−錫合金層、１４・・・厚い金層。

Claims (1)

    【実用新案登録請求の範囲】
  1. ポンディングパッドを形成する金属電極として、錫又は
    インジウム等の低融点金属と金との金属反応層と、この
    金属反応層上に金属を堆積形成させた積層電極を具備す
    ることを特徴とする半導体装置。　　−
JP1982192202U 1982-12-21 1982-12-21 半導体装置 Pending JPS5996849U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982192202U JPS5996849U (ja) 1982-12-21 1982-12-21 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982192202U JPS5996849U (ja) 1982-12-21 1982-12-21 半導体装置

Publications (1)

Publication Number Publication Date
JPS5996849U true JPS5996849U (ja) 1984-06-30

Family

ID=30413694

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982192202U Pending JPS5996849U (ja) 1982-12-21 1982-12-21 半導体装置

Country Status (1)

Country Link
JP (1) JPS5996849U (ja)

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