JPS622248U - - Google Patents

Info

Publication number
JPS622248U
JPS622248U JP1985092498U JP9249885U JPS622248U JP S622248 U JPS622248 U JP S622248U JP 1985092498 U JP1985092498 U JP 1985092498U JP 9249885 U JP9249885 U JP 9249885U JP S622248 U JPS622248 U JP S622248U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit chip
bonding
fixed
bonding pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985092498U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985092498U priority Critical patent/JPS622248U/ja
Publication of JPS622248U publication Critical patent/JPS622248U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図は本考案の第一の実施例を示す斜視図、
第２図は第１図のＡ―Ａ断面図、第３図は本考案
の他の実施例を示す斜視図である。 １，２……集積回路チツプ、３……集積回路パ
ツケージ、４ａ，４ｂ，５ａ，５ｂ……ボンデイ
ングパツド、６ａ，６ｂ……ボンデイングワイヤ
、７，８，９，１０……小形集積回路チツプ、１
１，１２，１３，２１，２２……半田バンプ、１
３……半導体ウエハ、１４……大形集積回路チツ
プ、１５，１６，２５，２６……導体ランド。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半田付け可能な複数個の第一の導体ランドを有
    し、第一の論理回路を構成する第一の集積回路チ
    ツプと、前記第一の導体ランドをおのおの半田接
    続される複数個の第二の導体ランドおよび複数個
    の第一のボンデングパツドを表面に配設され、前
    記第一の集積回路チツプを前記半田接続により表
    面上に固定し、第二の論理回路を構成する第二の
    集積回路チツプと、前記第二の集積回路チツプを
    表面に固定され、複数個のボンデイングワイヤで
    前記第一のボンデングパツドを接続される第二の
    ボンデイングパツドを有する集積回路パツケージ
    とを具備することを特徴とする集積回路装置。
JP1985092498U 1985-06-19 1985-06-19 Pending JPS622248U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985092498U JPS622248U (ja) 1985-06-19 1985-06-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985092498U JPS622248U (ja) 1985-06-19 1985-06-19

Publications (1)

Publication Number Publication Date
JPS622248U true JPS622248U (ja) 1987-01-08

Family

ID=30649351

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985092498U Pending JPS622248U (ja) 1985-06-19 1985-06-19

Country Status (1)

Country Link
JP (1) JPS622248U (ja)

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