JPS592142U - 半導体集積回路 - Google Patents

半導体集積回路

Info

Publication number
JPS592142U
JPS592142U JP1983059067U JP5906783U JPS592142U JP S592142 U JPS592142 U JP S592142U JP 1983059067 U JP1983059067 U JP 1983059067U JP 5906783 U JP5906783 U JP 5906783U JP S592142 U JPS592142 U JP S592142U
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor integrated
5n1zn
utility
main component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983059067U
Other languages
English (en)
Inventor
小口　幸一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP1983059067U priority Critical patent/JPS592142U/ja
Publication of JPS592142U publication Critical patent/JPS592142U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は従来のフェイスダウン用ＩＣの電極部分を示す
概観図。第２７図ａ、　　ｂは本考案によるフェイスダ
ウン用ＩＣの製造方法を説明する説明図。 １・・・シリコン基板、２・・・酸化膜、３・・・アル
ミニウム薄膜、４・・・パッシベーション被膜、５・・
・多層金属層、６・・・ハンダパップ、７・・・印刷さ
れたハンダバンプ。

Claims (1)

    【実用新案登録請求の範囲】
  1. アルミニウムポンディングパッド上に、５ｎ１Ｚｎを主
    成分とするハンダペーストによりハンダバンブが形成さ
    れた半導体集積回路。
JP1983059067U 1983-04-20 1983-04-20 半導体集積回路 Pending JPS592142U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983059067U JPS592142U (ja) 1983-04-20 1983-04-20 半導体集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983059067U JPS592142U (ja) 1983-04-20 1983-04-20 半導体集積回路

Publications (1)

Publication Number Publication Date
JPS592142U true JPS592142U (ja) 1984-01-09

Family

ID=30189327

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983059067U Pending JPS592142U (ja) 1983-04-20 1983-04-20 半導体集積回路

Country Status (1)

Country Link
JP (1) JPS592142U (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6112949A (ja) * 1984-06-25 1986-01-21 東レ株式会社 スパンライク加工糸
JPH0267731A (ja) * 1988-09-02 1990-03-07 Toshiba Corp はんだバンプ形半導体装置とその製造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51117574A (en) * 1975-04-08 1976-10-15 Seiko Epson Corp Semiconductor equipment

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51117574A (en) * 1975-04-08 1976-10-15 Seiko Epson Corp Semiconductor equipment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6112949A (ja) * 1984-06-25 1986-01-21 東レ株式会社 スパンライク加工糸
JPH0267731A (ja) * 1988-09-02 1990-03-07 Toshiba Corp はんだバンプ形半導体装置とその製造方法

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