EP1583407B1 - Mehrschichtige Leiterplatte mit gefüllten Kontaktlöchern - Google Patents

Mehrschichtige Leiterplatte mit gefüllten Kontaktlöchern Download PDF

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Publication number
EP1583407B1
EP1583407B1 EP20050012908 EP05012908A EP1583407B1 EP 1583407 B1 EP1583407 B1 EP 1583407B1 EP 20050012908 EP20050012908 EP 20050012908 EP 05012908 A EP05012908 A EP 05012908A EP 1583407 B1 EP1583407 B1 EP 1583407B1
Authority
EP
European Patent Office
Prior art keywords
layer
viahole
wiring board
printed wiring
multilayer printed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP20050012908
Other languages
English (en)
French (fr)
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EP1583407A1 (de
Inventor
Seiji Shirai
Kenichi Shimada
Motoo Asai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP10045397A external-priority patent/JPH11243277A/ja
Priority claimed from JP10045398A external-priority patent/JPH11243278A/ja
Priority claimed from JP10045396A external-priority patent/JPH11243280A/ja
Priority claimed from JP10045399A external-priority patent/JPH11243279A/ja
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to EP20070008979 priority Critical patent/EP1811825A1/de
Publication of EP1583407A1 publication Critical patent/EP1583407A1/de
Application granted granted Critical
Publication of EP1583407B1 publication Critical patent/EP1583407B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/421—Blind plated via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0129—Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/015—Fluoropolymer, e.g. polytetrafluoroethylene [PTFE]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0275—Fibers and reinforcement materials
    • H05K2201/0278—Polymeric fibers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09745—Recess in conductor, e.g. in pad or in metallic substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/381—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24273—Structurally defined web or sheet [e.g., overall dimension, etc.] including aperture
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24273—Structurally defined web or sheet [e.g., overall dimension, etc.] including aperture
    • Y10T428/24322—Composite web or sheet
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/31504—Composite [nonstructural laminate]
    • Y10T428/31678—Of metal
    • Y10T428/31681—Next to polyester, polyamide or polyimide [e.g., alkyd, glue, or nylon, etc.]

Definitions

  • the present invention relates to a multilayer printed wiring board having a filled viahole structure, and more particularly to a multilayer printed wiring board adapted to assure an outstandingly secure adhesion between a conductor circuitry layer and an interlaminar insulative resin layer and form a fine conductor circuit pattern.
  • the multilayer printed wiring board includes a build-up multilayer printed wiring board in which conductor circuitry layers and insulative resin layers are alternately formed one on another and inner and outer ones of the conductor circuitry layers are electrically connected to each other by viaholes formed in the insulative resin layers.
  • the viaholes in such a multilayer printed wiring board are formed by depositing a plating metal film on the inner wall and bottom of each of fine holes formed through the interlaminar insulative resin layers.
  • Such a multilayer printed wiring board is known from document EP-A-0743812.
  • the multilayer printed wiring board having such viaholes formed through them are not advantageous in that the metal deposit is likely to break due to its precipitation or a heat cycle.
  • it has recently been proposed to fill the viaholes with a platingmetal this structure will be referred to as "filled viahole structure” henceforth.
  • filled viahole structures are known from the disclosure, for example, in the Japanese unexamined patent publication Nos. Hei 2-188992, Hei 3-3298 and Hei 7-34048.
  • the multilayer printed wiring board having the filled viahole structure is however disadvantageous in that a surface portion of the plating metal exposed outside the hole for viahole (the surface will be referred to as "viahole surface” henceforth) is easily depressible. If an interlaminar rein insulating layer is formed on a conductor circuitry layer irrespectively of such a depression existent on the viahole surface, a corresponding depression will develop on the surface of the interlaminar insulative resin layer, and cause the plating metal film to break and also a trouble in mounting electronic parts on the wiring board.
  • the viahole surface where such a depression or concavity exists or is likely to exist can be flattened by applying an interlaminar resin more than once.
  • the application of the interlaminar resin will lead to a greater thickness of the interlaminar insulative resin layer just above the depression on the viahole surface than that of the interlaminar insulative resin layer on the conductor circuitry layer.
  • the interlaminar resin will partially remain inside the hole to lower the electrical connection reliability of the viahole.
  • the residual resin is likely tooccur since it is difficult to set different exposure and development conditions for the viahole surface from those for the conductor circuitry layer surface.
  • a plating conductor or metal is filled in a hole for viahole so that a conductor circuitry layer has a thickness more than a half of the viahole diameter and thus the conductor circuitry layer surface is at a same level as the viahole surface.
  • the inner wall of the hole formed in an interlaminar insulative resin layer should be plated with a thick layer of metal or conductor and thus a conductor circuitry layer formed along with the plating metal on the viahole will also be thick.
  • the plating resin should also be correspondingly thicker.
  • a plating metal is filled in a hole for viahole, a larger stress will be caused by heat cycle than in a viahole formed just by plating an inner wall and bottom of a hole, so that a crack is likely to occur first in the viahole and then spread to an interlaminar insulative resin layer.
  • an electroless plating method is used to fill the plating metal into the hole for viahole.
  • the plating layer applied by the electroless plating is harder and less malleable than a one applied by the electroplating. Therefore, the plating layer is likely to crack under a thermal shock or due to heat cycle.
  • the boundary between the electroless plating and electroplating layers is flat so that both the plating layers are separable from each other under a thermal shock or due to heat cycle.
  • a plating resist has to be formed before a hole for viahole is filled with a metal by the electroplating.
  • the plating resist is formed on the electroless plating layer, the plating resist is easily separable and an inter-pattern shortcircuit will possibly take place.
  • the present invention has a primary object to overcome the above-mentioned drawbacks of the prior art by providing a multilayer printed wiring board having a filled viahole structure adapted to form a fine conductor circuit pattern and provide a highly reliable electrical connection between conductive circuitry layers.
  • the present invention has another object to provide a multilayer printed wiring board having a filled viahole structure adapted to assure a highly secure adhesion between a conductor circuitry layer and an interlaminar insulative resin layer and which will not crack even under a thermal shock or due to heat cycle.
  • a build-up multilayer printed wiring board with the features of claim 1, said board having conductor circuitry layers and interlaminar insulative resin layers deposited alternately one on another, the interlaminar insulative resin layers having formed through them holes each filled with a plating layer to form a viahole, the hole in the interlaminar insulative resin layer having at least an inner wall thereof roughened, the roughened inner wall of the hole being covered with an electroless plating layer, and an inner space of the hole defined by the electroless plating layer being filled with an electroplating layer to form the viahole.
  • the electroless plating layer harder than the electroplating layer is formed over the inner wall of the hole.
  • the electroless plating layer bites, like anchor, the roughened surface, so it is not easily broken even if applied with a separating force.
  • the adhesion between the viahole and interlaminar insulative resin layer is improved.
  • the electroplating layer having a larger malleability than the electroless plating layer fills the major part of the hole, the electroplating layer will flexibly follow the expansion and shrinkage of the interlaminar insulative resin layer, thus the layers can be prevented from being cracked under a thermal shock or due to heat cycle.
  • an electroless plating layer formed on the roughened surface will have a correspondingly roughened surface.
  • the roughened surface or surface irregularity provides an effect of anchoring to assure a strong adhesion to the electroplating layer. Therefore, there will not occur any separation between the electroless plating layer and electroplating layer even under a thermal shock or due to heat cycle.
  • a plating resist applied on the roughened surface including the inner wall of the hole in the interlaminar insulative resin layer will have a close contact with the irregular surface of the electroless plating layer, and thus it will not easily be separated from the electroless plating layer surface. Therefore, there will not arise a shortcircuit between the conductor circuitry layers in the process of manufacturing a printed wiring board by the semi-additive method.
  • the viahole surface is not depressed and so the surface of the interlaminar insulative resin layer is very flat, a line breaking due to a depression can be avoided , and IC chips, etc. can be easily mounted on the wiring board without any inconvenience.
  • the interlaminar insulative resin layer on the viahole and conductive circuitry layer is uniformly thick, the resin will less reside when a hole for viahole is formed in the resin layer.
  • the conductor circuitry layer is less than the half of the viahole diameter, even when the hole for the viahole is filled with the plating metal to form a viahole, the conductor circuitry layer will have an increased thickness, so the plating resin layer can be thin, which allows to form a finer conductor circuit pattern.
  • the inner wall of the hole in the interlaminar insulative resin layer is roughened, which will improve the adhesion between the viahole formed from a filled plating metal and the interlaminar insulative resin layer.
  • the viahole is connected to the roughened surface of the inner conductor circuitry layer. Since the roughened surface improve the contact and thus adhesion between the circuitry layer and viahole, the circuitry layer and viahole will not easily be separated from each other at their boundary even at a high temperature and humidity or by heat cycle.
  • Roughening the conductor circuitry layer if applied, will advantageously prevent a crack which would develop first at the boundary between the circuitry layer and interlaminar insulative resin layer and then perpendicularly towards the interlaminar insulative resin layer.
  • the circuitry layer surface roughening should preferably be limited to a depth of 1 to 10 ⁇ m. A deeper surface roughening will cause an inter-layer shortcircuit while a shallower surface roughening will degrade the inter-layer adhesion.
  • the roughening should preferably be done by oxidation (blackening), and reduction, of the surface of the circuitry layer, spraying an aqueous mixed solution of an organic acid and a cupric complex, or by electroless copper-nickel- phosphorus plating.
  • the oxidation (blackening) and reduction use an oxidation bath of NaOH (20 g/l), NaClO 2 (50 g/l) and Na 3 PO 4 (15.0 g/l),l and a reduction bath of NaOH (2.7 g/l) and HaBH 4 (1.0 g/l), respectively.
  • the aqueous mixed solution of organic acid and cupric complex will dissolve a metal foil such as copper forming the lower conductor circuitry layer in the existence of oxygen, namely, during spraying or bubbling as will be discussed below: Cu + Cu(II)An ⁇ 2Cu(I)An/ 2 2cu(I)An/ 2 + n/4O 2 + nAH (aeration) ⁇ 2Cu(II)An + n/2H 2 O
  • A Complexing agent
  • n Coordination number.
  • the cupric secondary complex used in the above method should preferably be a cupric secondary complex of any one of azoles.
  • the cupric secondary complex of an azole is used to oxidize a metal copper.
  • One should preferably be diazole, triazole or tetrazole, and more preferably, imidazole, 2-methylimidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole or 2-undecylimidazole.
  • the cupric secondary complex of azole should preferably be used in an amount of 1 to 15 % by weight. In this range of content, the cupric secondary complex shows an outstanding solubility and stability.
  • the organic acid is used in the aqueous solution to dissolve the copper oxide, and should preferably be at least one selected from formic acid, acetic acid, propionic acid, butyric acid, valerianic acid, caproic acid, acrylic acid, crotonic acid, oxalic acid, malonic acid, succinic acid, glutaric acid, maleic acid, benzoic acid, glycolic acid, lactic acid, malic acid, and sulfamic acid.
  • the content of the organic acid should preferably be 0.1 to 30% by weight in order to maintain the solubility of the copper oxide and stability of the dissolved copper oxide.
  • a cuprous complex produced will be dis solved under the action of the acid and combined with an oxygen to produce a cupric secondary complex which will contribute to copper oxidation again.
  • a halogen for example, fluorine ion, chlorine ion or bromine ion may be added to an etchant or etching solution of the organic acid and cupric complex.
  • the halogen ion may a one to which hydrochloric acid, sodium chloride, etc. is added.
  • the content of the halogen ion should preferably be 0.01 to 20 % by weight. In this range of content, the layer surface roughened by attacking by the etchant will provide a secure adhesion between the conductor circuitry layer and interlaminar insulative resin layer.
  • the etchant of the organic acid and cupric secondary complex is prepared by dissolving a cupric secondary complex of an azole and an organic acid (containing a halogen ion as necessary) in water.
  • a plating bath should preferably be used which is composed of 1 to 40 g/l of copper sulfate, 0.1 to 6.0 g/l of nickel sulfate, 10 to 20 g/l of citric acid, 10 to 100 g/l of hypophosphite, 10 to 40 g/l of boric acid and 0.01 to 10 g/l of a surfactant.
  • a further viahole should preferably be formed on one filled viahole to eliminate any viahole-caused dead space for wiring, which will implement a higher density of wiring.
  • the multilayer printed wiring board can use, as the interlaminar insulative resin layer, a thermosetting resin, thermoplastic resin, or a composite of thermosetting and thermoplastic resins.
  • the interlaminar insulative resin layer should be formed from a composite of thermosetting and thermoplastic resins.
  • thermosetting resin may be a one selected from epoxy resin, polyimide resin, phenol resin, thermosetting polyphenylether (PPE), etc.
  • the thermoplastic resin may be a one selected from fluororesins such as polytetrafluoroethylene (PTFE), polyethylene terephthalate (PET), polysulfone (PSF), polyphenylene sulfide (PPS), thermoplastic polyphenylene ether (PPE), polyether sulfone (PES), polyether imide (PEI), polyphenylene sulfon (PPES), tetrafluoroethylene hexafluoropropylene copolymer(FEP), tetra fluoroethylene perfluoroalcoxy copolymer (PFA), polyethylene naphthalate (PEN), polyether ether ketone (PEEK), polyolefin, etc.
  • fluororesins such as polytetrafluoroethylene (PTFE), polyethylene terephthalate (PET), polysulfone (PSF), polyphenylene sulfide (PPS), thermoplastic polyphenylene ether (PPE), polyether
  • the composite of thermosetting and thermoplastic resins may be a composite of epoxy resin with PES, PSF, PPS or PPES, or similar.
  • This embodiment should preferably use a composite of a fluororesin fiber cloth and a thermosetting resin charged in voids in the cloth since the composite shows a low dielectric constant and high dimensional stability.
  • thermosetting resin should preferably be at least a one selected from epoxy resin, polyimide resin, polyamide resin and phenol resin.
  • the fluororesin fabric cloth should preferably be a texture or nonwoven fabric made from the fluororesin fibers.
  • the nonwoven fabric is produced by forming a sheet from short or long fluororesin fibers and a binder and heating the sheet to fuse the fibers to each other.
  • this embodiment of the present invention can use an adhesive for use in the electroless plating as the interlaminar insulative resin layer.
  • the electroless plating adhesive should optimally be prepared by dispersing cured heat-resistant resin particles soluble in acid or oxidizing agent into a non-cured heat-resistant resin which will be made insoluble in acid or oxidizing agent by curing.
  • This electroless plating adhesive is most suitably usable because the heat-resistant resin particles can be dissolved and removed in the presence of an acid or oxidant to have formed thereon a roughened surface which can securely anchor an adjoining layer.
  • the electroless plating adhesive namely, the cured heat-resistant resin particles, should preferably be at least a one selected from a heat-resistant resin powder of 10 ⁇ m or less in mean particle size, agglomerate produced by coagulating heat-resistant resin particles of 2 ⁇ m or less in mean particle size, mixture of a heat-resistant resin powder of 2 to 10 ⁇ m or less in mean particle size and a heat-resistant resin powder of 2 ⁇ m or less in mean particle size, dummy particles produced by depositing at least a one selected from a heat-resistant resin powder or inorganic powder of 2 ⁇ m or less in mean particle size on the surface of a heat-resistant resin powder of 2 to 10 ⁇ m in mean particle size, mixture of a heat-resistant resin powder of 0.1 to 0.8 ⁇ m in mean particle size and a heat-resistant resin powder of over 0. 8 ⁇ m and under 2 ⁇ m in mean particle size, and a heat-resistant resin powder of 0.1 to 1.0 ⁇ m in mean particle size.
  • the heat-resistant resin used in the electroless plating adhesive may be any one of the aforementioned thermosetting resin, thermoplastic resin and composite of thermosetting and thermoplastic resins. Particularly, the composite of thermosetting and thermoplastic resins is optimally usable for this embodiment of the present invention.
  • the multilayer printed wiring board according to the first embodiment of the present invention has been described in the foregoing. This printed wiring board is manufactured as will be described herebelow with reference to FIGS. 1 and 2.
  • solder foil is attached to a prepreg, and the solder foil is etched with only a portion thereof corresponding to the hole to form a solder pattern which will be a solder carrier film.
  • solder carrier film is attached on the flux and heated to transfer the solder.
  • solder printing method a printing mask (metallic) having through-holes formed in positions corresponding to the solder pads is placed on the wiring substrate and a solder paste is printed on the mask and heated.
  • a solder bump is formed on the filled viahole.
  • the viahole since the viahole is not filled, a larger amount of solder paste is required to form a solder bump as high as a solder bump of a flat solder pad. Namely, the hole in the printing mask has to be large. According to this embodiment of the present invention, however, since the viahole is filled, the solder paste may be applied in a uniform amount and the holes in the printing mask may have a same size.
  • the second embodiment of the present invention will further be discussed herebelow.
  • the interlaminar insulative resin layers having formed through them holes each filled with a plating layer to form a viahole
  • the thickness of the conductor circuitry layer is less than a half of the viahole diameter and less than 25 ⁇ m.
  • the thickness of the plating conductor forming the conductor circuitry layer can be less than the half of the viahole and less than 25 ⁇ m.
  • the thickness of the plating conductor forming the conductor circuitry layer can be less than the half of the viahole and less than 25 ⁇ m.
  • the conductor circuitry layer has the thickness less than the half of the opening diameter of the viahole and less than 25 ⁇ m, the area of contact of the edge of the conductor circuitry layer with the interlaminar insulative resin layer is reduced correspondingly. Therefore, the central portion of the viahole surface should preferably be depressed and roughened, whereby the adhesion between the conductor layer and interlaminar insulative resin layer can be improved and thus separation between them can be prevented. More specifically, a stress developed due to heat cycle can be dispersed so that the conductor and insulative layers can be prevented from being separated from each other.
  • thermosetting resin, thermoplastic resin and composite of thermosetting and thermoplastic resins may be selected from those having previously been described concerning the first embodiment, and so they will not be discussed any longer.
  • the multilayer printed wiring board having the aforementioned filled viahole structure according to the second embodiment are manufactured as will be described below with reference to FIGS. 1 and 2.
  • the manufacturing process is substantially same as that for the first embodiment and thus includes the previously mentioned steps (1) to (14).
  • the electroplating layer should preferably be formed to a thickness of 5 to 20 ⁇ m so that the conductor circuitry layer has a thickness less than a half of the viahole diameter and less than 25 ⁇ m.
  • the electroless plating layer harder than the electroplating layer is formed over the inner wall of the hole.
  • the electroless plating layer bites, like anchor, the roughened surface, so it is not easily broken even when a separating force is applied, and the adhesion between the viahole and interlaminar insulative resin layer is improved.
  • the electroplating layer having a larger malleability than the electroless plating layer fills the major part of the hole, the electroplating layer will flexibly follow the expansion and shrinkage of the interlaminar insulative resin layer, thus the layers can be prevented from being cracked under a thermal shock or due to heat cycle.
  • the inner wall of the hole in the interlaminar insulative resin layer is roughened, there is provided an improved adhesion between the viahole and interlaminar insulative resin layer.
  • the electroless plating layer formed on the roughened surface is so thin as to follow the irregularity of the roughened surface. This surface irregularity serves as anchor to provide a strong adhesion to an electroplating layer. Therefore, the electroless plating layer and electroplating layer will not be separated from each other even due to heat cycle or under a thermal shock.
  • the roughened surface is electroless plated, and further a plating resist is applied to the electroless plating layer.
  • the plating resist applied on the roughened surface will close adhere to the irregular surface of the electroless plating layer, and thus it will not easily be separated from the electroless plating layer surface. Therefore, there will not arise a shortcircuit between the conductor circuitry layers in the process of manufacturing the printed wiring board by the semi-additive method.
  • the electroless plating layer forming the above-mentioned conductor circuit should preferably be 0.1 to 5 ⁇ m, and more preferably 1 to 5 ⁇ m for a thickness too larger than 5 ⁇ m will not assure to sufficiently follow the shape of the roughened surface of the interlaminar insulative resin layer while a thickness too smaller than 1 ⁇ m will lower the separating or peeling strength and cause a large resistance which will interfere with a subsequent electroplating, so that the plating layer thickness will not be uniform.
  • the electroplating layer forming the conductor circuit should preferably have a thickness within a range of 5 to 30 ⁇ m, and more preferably a thickness ranging from 10 to 20 ⁇ m. This is because a larger thickness will cause the peeling strength to be lowerwhile a smaller thickness will increase the resistance, so that the electroplating will result in an uneven precipitation.
  • the multilayer printed wiring board having the aforementioned filled viahole structure according to the third embodiment is manufactured as will be discussed herebelow with reference to FIGS. 1 and 2.
  • the manufacturing process is substantially same as that for the first embodiment and thus includes the previously mentioned steps (1) to (14).
  • the electroplating layer should preferably be 5 to 20 ⁇ m thick so that the conductor circuitry layer is less than a half of the viahole diameter.
  • the plating solution composition, plating temperature, dipping length of time and agitating conditions should preferably be controlled to depress the central portion of the plating layer exposed out of the hole that forms the viahole.
  • the depression should preferably have a size less than the thickness of the conductor layer, and more preferably be 20 ⁇ m or less. This is because a bigger depression will result in a larger thickness of the interlaminar insulative resin layer formed on the depression than that of the resin layer formed on the other conductor layers. When the resin layer is exposed, developed and lased , it is likely to partially remain on the depression in the viahole, which will lower the electrical connection reliability of the viahole.
  • the interlaminar insulative resin layer is formed from a composite of fluororesin and heat-resistant thermoplastic resin, composite of fluororesin and thermosetting resin, or a composite of thermosetting resin and heat-resistant resin.
  • the interlaminar insulative resin layer in which the viahole is provided is formed from a highly tough composite of fluororesin and heat-resistant thermoplastic resin, or a highly tough composite of fluororesin and thermosetting resin. So, even if the viahole is made from a hole filled with a plating layer, since the metal layer is thermally expanded during heat cycle, no crack will develop first at the viahole. Also, the fluororesin has so low a dielectric constant that signal will be propagated with no delay.
  • the interlaminar insulative resin layer in which the viahole is formed should preferably be formed from a composite of fluororesin and heat-resistant thermoplastic resin, or a composite of fluororesin and thermosetting resin.
  • the fluororesin should preferably be a polytetrafluoroethylene since it is a most versatile fluororesin.
  • the heat-resistant thermoplastic resin should preferably be a one which can be thermally decomposed at a temperature higher than 250°C and that is selected from fluororesins such as polytetrafluoroethylene (PTFE),polyethylene terephthalate (PET),polysulfone (PSF),polyphenylene sulfide (PPS), thermoplastic polyphenylene ether (PPE), polyether sulfone (PES), polyether imide (PEI), polyphenylene sulfon (PPES), tetrafluoroethylene hexafluoropropylene copolymer (FEP), tetrafluoroethylene perfluoroalcoxy copolymer (PFA), polyethylene naphthalate (PEN), polyether ether ketone (PEEK), polyolefin, etc.
  • fluororesins such as polytetrafluoroethylene (PTFE),polyethylene terephthalate (PET),polysulfone (
  • thermosetting resin may be epoxy resin, polyimide resin, phenol resin, thermosetting polyphenylene ether (PPE), or similar.
  • the composite of fluororesin and thermosetting resin should preferably be a composite of fluororesin fabric cloth and thermosetting resin charged in voids in the cloth.
  • the a fluororesin fabric cloth should preferably be a texture or nonwoven fabric made from the fluororesin fibers.
  • the nonwoven fabric is produced by forming a sheet from short or long fluororesin fibers and a binder and heating the sheet to fuse the fibers to each other.
  • thermosetting resin should preferably be at least a one selected from epoxy resin, polyimide resin, polyamide resin and phenol resin.
  • the composite of thermosetting and thermoplastic resins may be a composite of epoxy resin with PES, PSP, PPS or PPES, or similar.
  • the multilayer printed wiring board according to the fourth example is manufactured as will be described herebelow with reference to FIGS. 3 and 4.
  • the manufacturing process is substantially same as that for the first embodiment and thus includes the previously mentioned steps (1) to (14).
  • a composite of fluororesin and heat-resistant thermoplastic resin, composite of fluororesin and thermosetting resin or a composite of thermosetting and thermoplastic resins is used as the interlaminar insulative resin layer.
  • an electroless plating adhesive using the composite as resin matrix should preferably be used.
  • the hole for the viahole is formed by exposing, developing and then thermally curing the resin layer.
  • the resin is a composite of fluororesin and heat-resistant thermoplastic resin, composite of fluororesin and thermosetting resin or a composite of thermosetting and thermoplastic resins
  • the hole for the viahole is formed by thermosetting the resin layer and then by lasing drilling.
  • the ratio D/T 1 between the viahole diameter (D) and interlaminar insulative resin layer thickness (T 1 ) should preferably be within a range of 1 to 4. This is because if the ratio D/T 1 is less than 1, the electroplating solution will not enter the hole while the ratio over 4 will not allow the hole to sufficiently be filled with a plating metal.
  • the surface of the interlaminar insulative resin layer should preferably be roughened by plasma etching or the like for this roughening will improve the adhesion to the plating layer.
  • the epoxy resin particles existent on the surface of the cured adhesive layer are removed by decomposing or dissolving with an acid or oxidant to rough the surface of the adhesive layer.
  • examples 1 to 9 and comparative examples 1 to 8 of multilayer printed wiring boards were prepared through the steps (1) to (11) of the 14 steps having been described in the foregoing, not yet including the step at which the solder bump is formed.
  • Example 11 was prepared through all the steps (1) to (14). Themultilayer printed wiring boards thus prepared will further be described in detail herebelow:
  • compositions prepared through the following steps 1 to 3 were mixed together and agitated to prepare an electroless plating adhesive.
  • a multilayer printed wiring board was prepared in the same manner as the aforementioned example 1 except that an interlaminar insulative resin layer was formed by attaching a fluororesin film of 20 ⁇ m in thickness to the layer by thermo-compression bonding and holes for viaholes of 60 ⁇ m in diameter were formed by irradiating ultraviolet laser.
  • a multilayer printed wiring board was produced in the same manner as the aforementioned example 1 except that a conductor circuit was made only of an electroless plating layer of 25 ⁇ m in thickness and viaholes were formed by dipping for 11 hours in en electroless plating aqueous solution composed of 0.06 mol/l of copper sulfide, 0.3 mol/l of formalin, 0.35 mol/l of NaOH, 0.35 mol/l of EDTA and a small amount of additive at 75°C and having a pH of 12.4.
  • the holes in the interlaminar insulative resin layer were found filled with the plating layer, but a depression of 20 to 25 m was found in the central portion of the plating layer.
  • a multilayer printed wiring board was produced. More particularly, the steps (1) to (5) for the embodiment 1 were repeated to process a substrate and then the substrate was dipped in an electroless plating solution prepared from an aqueous solution composed of 0.05 mol/l of copper sulfide, 0.30 mol/l of formalin, 0.35 mol/l of sodium hydroxide, and 0.35 mol/l of ethylenediaminetetraacetic acid (EDTA) to form a plating layer of 40 ⁇ m in thickness.
  • an electroless plating solution prepared from an aqueous solution composed of 0.05 mol/l of copper sulfide, 0.30 mol/l of formalin, 0.35 mol/l of sodium hydroxide, and 0.35 mol/l of ethylenediaminetetraacetic acid (EDTA) to form a plating layer of 40 ⁇ m in thickness.
  • etching resist 25/25 ⁇ m on the substrate.
  • the substrate was dipped in a mixed solution of sulfuric acid and hydrogen peroxide.
  • the conductor circuitry layer was undercut and separated. Therefore, the comparative example 2 was not evaluated.
  • the examples 1 to 3 and comparative example 1 were evaluated as to 1 surface flatness of their interlaminar insulative resin layer and 2 electrical connection reliability of the viahole.
  • the above item 1 surface flatness, was evaluated by judging whether a depression developed on a first applied interlaminar insulative resin layer.
  • the item 2 electrical connection reliability of the viahole, was evaluated by checking, using a probe, whether a further viahole formed on a viahole already formed showed a poor electrical continuity. The evaluation results are shown in Table 1.
  • the examples 1, 2 and 3 are superior in surface flatness of the interlaminar insulative resin layer. Even when the further viahole is provided on the inner one, a circuit pattern breaking due to a depression is not observed, namely, the examples Table 1 Depression on interlaminar insulative resin layer Poor electrical continuity
  • Example 1 No No Example 2 - No Example 3 - No Comparative example 1 Yes No 1 to 3 have a high electrical connection reliability of the viahole, and IC chip and other devices can easily be mounted on the wiring boards with no inconvenience. Further, even when mass-produced, the examples 1 to 3 will show a high electrical connection reliability of the viaholes.
  • the first embodiment of the present invention provides a multilayer printed wiring board having a filled viahole structure enabling a fine circuit pattern to be formed and showing superior surface flatness and high electrical connection reliability of the viahole.
  • Aqueous electroplating solution CuSO 4 ⁇ 5H 2 O 60 g/l Leveling agent (HL by ATOTTECK) 40 ml/l Sulfuric acid 190 g/l Brightening agent (UV by ATOTTECH) 0.5 ml/l Chlorine ion 40 ppm
  • Electroplating conditions Bubbling 3.0 liters/min Current density 0.5 A/dm 2 Set current value 0.18 A Plating length of time 100 min (8) The plating resist layer 8 was separated and removed, and then the electroless plating layer 7 under the plating resist layer 8 was dissolved for removal in an etching solution composed of a mixture of sulfuric acid and hydrogen peroxide, sodium persulfate, ammoniumpersulfate, etc.
  • a multilayer printed wiring board was produced by repeating the steps (1) to (3) for the example 3, and further processing the substrate as follows:
  • a multilayer printed wiring board was produced. More particularly, the steps (1) to (5) for the embodiment 5 were repeated and then the substrate was dipped in an electroless plating solution prepared from an aqueous solution composed of 0.05 mol/l of copper sulfide, 0.30 mol/l of formalin, 0. 35 mol/l of sodium hydroxide, and 0.35 mol/l of ethylenediaminetetraacetic acid (EDTA) to form a plating layer of 40 ⁇ m in thickness.
  • an electroless plating solution prepared from an aqueous solution composed of 0.05 mol/l of copper sulfide, 0.30 mol/l of formalin, 0. 35 mol/l of sodium hydroxide, and 0.35 mol/l of ethylenediaminetetraacetic acid (EDTA) to form a plating layer of 40 ⁇ m in thickness.
  • EDTA ethylenediaminetetraacetic acid
  • the substrate was dipped in a mixed solution of sulfuric acid and hydrogen peroxide.
  • the conductor circuitry layer was undercut and separated.
  • Aqueous electroplating solution CuSO 4 ⁇ 5H 2 O 60 g/l Leveling agent (HL by ATOTTECH) 40 ml/l Sulfuric acid 190 g/l Brightening agent (UV by ATOTTECH) 0.5 ml/l Chlorine ion 40 ppm
  • Electroplating conditions Bubbling 3.0 liters/min Current density 0.5 A/dm 2 Set current value 0.18 A Plating length of time 100 min (8) The plating resist layer 8 was separated and removed, and then the electroless plating layer 7 under the plating resist layer 8 was dissolved for removal in an etching solution composed of a mixture of sulfuric acid and hydrogen peroxide, sodium persulfate, ammoniumpersulfate, etc.
  • a multilayer printed wiring board was produced by repeating the steps (1) to (3) for the example 2, and further processing the substrate as follows:
  • a multilayer printed wiring board was produced similarly to the embodiment as disclosed in the Japanese unexamined patent publication No. hei 2-188992.
  • the holes for viaholes were filled only with the electroless plating layer to form the viaholes.
  • a multilayer printed wiring board was produced by repeating the steps (1) to (3) for the example 6 and further processing the substrate as follows.
  • the substrate was dipped in an electroless plating solution prepared from an aqueous solution composed of 0.05 mol/l of copper sulfide, 0.30 mol/l of formalin, 0.35 mol/l of sodium hydroxide, and 0.35 mol/l of ethylenediaminetetraacetic acid (EDTA) to form a plating layer of 1 ⁇ m in thickness.
  • an electroless plating solution prepared from an aqueous solution composed of 0.05 mol/l of copper sulfide, 0.30 mol/l of formalin, 0.35 mol/l of sodium hydroxide, and 0.35 mol/l of ethylenediaminetetraacetic acid (EDTA) to form a plating layer of 1 ⁇ m in thickness.
  • EDTA ethylenediaminetetraacetic acid
  • this multilayer printed wiring board had no roughed surface on the viahole.
  • the comparative example 5 showed a cracking in the viahole portion
  • the comparative example 6 showed a separation of the viahole portion
  • the examples 6 and 7 showed neither separation nor cracking at the viahole portion.
  • the third embodiment of the present invention provides a multilayer printed wiring board having a filled viahole structure in which the viahole is not easily separable and no crack takes place under a thermal shock or due to heat cycle.
  • a multilayer printed wiring board not according to the invention however, was produced of which the interlaminar insulative resin layer was made of a composite of fluororesin and heat-resistant thermoplastic resin, through a process including the following steps: (1) An interlaminar insulative resin liquid was prepared by thermally fusing and mixing eight parts by weight of polyether sulfone (PES) and 92 parts by weight of fluororesin (Teflon by Du Pont) at 350°C. (2) A substrate 1 made of bismaleimide triazine (BT) and having a conductor circuitry layer 2 formed on either surface thereof (as in FIG.
  • PES polyether sulfone
  • Teflon by Du Pont fluororesin
  • a plating resist layer 8 was formed on the electroless plating copper layer 7 in the conventional manner (see FIG. 4(a)). (7) Next, a portion on which the plating resist layer 8 was not formed was electroplated under the following conditions to form an electroplating layer of 15 ⁇ m in thickness on the portion.
  • the layer 9 provided a conductor layer on which a conductor circuit was to be formed, and the electroplating layer 9 was filled in the hole to form a viahole 10 (as in FIG. 4(b)).
  • Aqueous electroplating solution CuSO 4 ⁇ 5H 2 O 60 g/l Leveling agent (HL by ATOTTECH) 40 ml/l Sulfuric acid 190 g/l Brightening agent (UV by ATOTTECH) 0.5 ml/l Chlorine ion 40 ppm
  • Electroplating conditions Bubbling 3.0 liters/min Current density 0.5 A/dm 2 Set current value 0.18 A Plating length of time 130 min (8) The plating resist layer 8 was separated and removed, and then the electroless plating copper layer 7 under the plating resist layer 8 was dissolved for removal in an etching solution composed of a mixture of sulfuric acid and hydrogen peroxide, sodium persulfate, ammoniumpersulfate, etc.
  • the viahole 10 had a flat surface, and the conductor circuitry layer surface was at a same level as the viahole surface.
  • a rough surface layer 3 was formed on the substrate. Further, the steps (3) to (8) were repeated to produce the multilayer printed wiring board (as in FIG. 4(c)).
  • a multilayer printed wiring board was produced of which the interlaminar insulative resin layer was made of a composite of fluororesin and thermosetting resin, by repeating the above steps (1) to (3) for the example 3 and further processing the substrate as follows:
  • a multilayer printed wiring board of which the interlaminar insulative resin layer was made of a composite of thermosetting and thermoplastic resins was produced by repeating the steps (1) to (6) for the example 1 and further processing the substrate as follows:
  • the viahole 10 had a flat surface, and the conductor surface was at a same level as the viahole surface.
  • a multilayer printed wiring board was produced of which the interlaminar insulative resin layer was made only of a thermosetting resin, as follows:
  • steps (2) to (9) for the example 10 were repeated to provide the multilayer printed wiring board.
  • a multilayer printed wiring board was produced in the same manner as for the example 8 except that no leveling agent and brightening agent were added to the electroplating solution. As a result, a plating layer could not sufficiently be filled in the holes for the viaholes.
  • the example 8 is highly resistant against violent temperature variation since its interlaminar insulative resin layer incorporates a fluororesin and thermoplastic resin.
  • the fourth embodiment of the present invention provides a multilayer printed wiring board having a filled viahole structure permitting to positively prevent line breakage in the wiring board and improved in resistance against violent temperature variation.
  • a multilayer printed wiring board was produced by repeating the steps (1) to (9) for the example 1, and further processing the substrate as follows:
  • a solder resist composition was prepared by mixing 46.67 parts by weight of a photosensitive oligomer (4000 in molecular weight) produced by acrylating 50% of epoxy group of a 60% by weight of cresol novolac type epoxy resin (by Nippon Kayaku Co., Ltd.)solved in DMDG (diethyleneglycoldimethylether), 6.666 parts by weight of a 80% by weight of bisphenol A type epoxy resin (EPICOAT 1001 by YUKA SHELL) solved in MEK (methyletylketone), 6.666 parts by weight of an epoxy resin of the same bisphenol A type (EPICOAT E-1001-B80 by YUKA SHELL), 1.6 parts by weight of imidazole (2E4MZ-CN by Shikoku Kasei Co.
  • a polyvalent acryl monomer being a photosensitive monomer R604 by Nippon Kayaku Co., Ltd.
  • a same polyfunctional acryl monomer DPE6A by KYOEISHA KAGAKU Co., Ltd.
  • leveling agent made from an acrylic ester polymer POLYFLOW No. 75 by KYOEISHA KAGAKU.
  • 2.0 parts by weight of an initiator IRGACURE I-907 by Ciba Geigy
  • 0.2 part by weight of photosensitizer DETX-S (by Nippon Kayaku Co., Ltd.) were added to the above mixture.
  • 0.6 part by weight of DMDG was added to the mixture to adjust the viscosity to 1.4 ⁇ 0.3 Pa ⁇ s at 25°C.
  • the viscosity of the solder resist composition was measured using a B-type viscometer (DVL-B by Tokyo Keiki). For 60 rpm, No. 4 rotor was used with the viscometer. For 6 rpm, No. 3 rotor was used.
  • the present invention provides a multilayer printed wiring board best suitable for forming a fine circuit pattern thereon, providing an excellent adhesion between the conductor circuit and interlaminar insulative resin layer and an outstanding resistance against cracking due to heat cycle.
  • the multilayer printed wiring board according to the present invention has an excellent applicability in many fields of art requiring a high performance and high packaging density of electronic parts.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Claims (6)

  1. Mehrschichtige Leiterplatte mit Leiter-Schaltungsschichten (2, 12) und isolierenden Harz-Zwischenschichten (4), die abwechselnd aufeinander abgeschieden sind, wobei durch die isolierenden Harz-Zwischenschichten (4) hindurch jeweils Löcher (5) ausgebildet sind, die gefüllt sind, um ein gefülltes Kontaktloch (10) auszubilden, und
    die Innenwand des Lochs (5) aufgeraut ist;
    die Oberflächen der inneren Leiter-Schaltung (2), die über das Kontaktloch miteinander verbunden sind, aufgeraut sind;
    die aufgeraute Innenwand und die aufgeraute Oberfläche (3) mit einer stromlos abgeschiedenen Schicht (7) bedeckt sind,
    dadurch gekennzeichnet, dass
    die stromlos abgeschiedene Schicht (7) aufgeraut ist und ein Innenraum der Löcher, der durch die stromlos abgeschiedene Schicht (7) begrenzt ist, mit einer durch Elektroplattieren abgeschiedenen Schicht (9) gefüllt ist.
  2. Mehrschichtige Leiterplatte nach Anspruch 1, wobei die Oberfläche der abgeschiedenen Schicht (9) sowie die Oberfläche der Leiter-Schaltung (12), die über das Loch für das Kontaktloch (10) freiliegt, aufgeraut sind.
  3. Mehrschichtige Leiterplatte nach einem der Ansprüche 1 oder 2, wobei ein weiteres Kontaktloch (20) an dem Kontaktloch (10) ausgebildet ist.
  4. Mehrschichtige Leiterplatte nach einem der Ansprüche 1 bis 3, wobei die isolierende Harz-Zwischenschicht (4), in der das Kontaktloch (10) ausgebildet ist, aus einem Thermoplastharz oder einem Verbundstoff aus Thermoplastharz und wärmehärtbarem Harz besteht.
  5. Mehrschichtige Leiterplatte nach einem der Ansprüche 1 bis 4, wobei das Verhältnis zwischen dem Durchmesser (D) des Kontaktlochs und der Dicke (4, T1) der isolierenden Harz-Zwischenschicht innerhalb eines Bereiches von 1 bis 4 liegt.
  6. Mehrschichtige Leiterplatte nach einem der Ansprüche 1 bis 5, wobei die Dicke (T2) der Leiter-Schaltungsschicht (1, 12) geringer ist als 25 µm.
EP20050012908 1998-02-26 1999-02-05 Mehrschichtige Leiterplatte mit gefüllten Kontaktlöchern Expired - Lifetime EP1583407B1 (de)

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EP20070008979 EP1811825A1 (de) 1998-02-26 1999-02-05 Mehrschichtige Leiterplatte mit gefüllten Kontaktlöchern

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
JP4539898 1998-02-26
JP10045397A JPH11243277A (ja) 1998-02-26 1998-02-26 フィルドビア構造を有する多層プリント配線板
JP10045398A JPH11243278A (ja) 1998-02-26 1998-02-26 フィルドビア構造を有する多層プリント配線板
JP4539998 1998-02-26
JP10045396A JPH11243280A (ja) 1998-02-26 1998-02-26 フィルドビア構造を有する多層プリント配線板
JP4539698 1998-02-26
JP4539798 1998-02-26
JP10045399A JPH11243279A (ja) 1998-02-26 1998-02-26 フィルドビア構造を有する多層プリント配線板
EP19990902842 EP1075172B1 (de) 1998-02-26 1999-02-05 Mehrschichtige leiterplatte mit einer struktur von gefüllten kontaktlöchern

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EP1583407B1 true EP1583407B1 (de) 2007-05-30

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EP20070008979 Withdrawn EP1811825A1 (de) 1998-02-26 1999-02-05 Mehrschichtige Leiterplatte mit gefüllten Kontaktlöchern
EP20050012908 Expired - Lifetime EP1583407B1 (de) 1998-02-26 1999-02-05 Mehrschichtige Leiterplatte mit gefüllten Kontaktlöchern
EP19990902842 Expired - Lifetime EP1075172B1 (de) 1998-02-26 1999-02-05 Mehrschichtige leiterplatte mit einer struktur von gefüllten kontaktlöchern

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US (6) US7071424B1 (de)
EP (4) EP1505859B1 (de)
KR (4) KR100906931B1 (de)
CN (2) CN100475005C (de)
DE (3) DE69928518T2 (de)
MY (1) MY129801A (de)
TW (1) TW404158B (de)
WO (1) WO1999044403A1 (de)

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EP1744609B1 (de) 1999-06-02 2012-12-12 Ibiden Co., Ltd. Gedruckte mehrlagige Schaltungsplatte und Verfahren zur Herstellung
WO2001011932A1 (en) 1999-08-06 2001-02-15 Ibiden Co., Ltd. Electroplating solution, method for fabricating multilayer printed wiring board using the solution, and multilayer printed wiring board
JP4062907B2 (ja) * 2001-11-12 2008-03-19 松下電器産業株式会社 回路基板およびその製造方法
JP4029759B2 (ja) * 2003-04-04 2008-01-09 株式会社デンソー 多層回路基板およびその製造方法
TW200521171A (en) 2003-12-26 2005-07-01 Toshiba Kk Resin particles and resin layer containing metal micro particles, its forming method and circuit base board
JP4426900B2 (ja) * 2004-05-10 2010-03-03 三井金属鉱業株式会社 プリント配線基板、その製造方法および半導体装置
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US8987603B2 (en) 2015-03-24
CN1585593A (zh) 2005-02-23
US8115111B2 (en) 2012-02-14
US20100101852A1 (en) 2010-04-29
EP1075172A1 (de) 2001-02-07
CN1168361C (zh) 2004-09-22
KR100633678B1 (ko) 2006-10-11
EP1075172B1 (de) 2005-11-23
DE69936235T2 (de) 2007-09-13
DE69936235D1 (de) 2007-07-12
US20080264686A1 (en) 2008-10-30
KR100906931B1 (ko) 2009-07-10
WO1999044403A1 (en) 1999-09-02
EP1505859A3 (de) 2005-02-16
KR20010041267A (ko) 2001-05-15
US7390974B2 (en) 2008-06-24
KR20080017496A (ko) 2008-02-26
US7622183B2 (en) 2009-11-24
US20120103680A1 (en) 2012-05-03
MY129801A (en) 2007-04-30
EP1075172A4 (de) 2003-08-13
DE69936892D1 (de) 2007-09-27
KR20060095785A (ko) 2006-09-01
US7071424B1 (en) 2006-07-04
DE69936892T2 (de) 2007-12-06
US7737366B2 (en) 2010-06-15
EP1583407A1 (de) 2005-10-05
CN100475005C (zh) 2009-04-01
EP1505859B1 (de) 2007-08-15
KR20080059680A (ko) 2008-06-30
US20050100720A1 (en) 2005-05-12
US20060159885A1 (en) 2006-07-20
DE69928518D1 (de) 2005-12-29
EP1505859A2 (de) 2005-02-09
TW404158B (en) 2000-09-01
DE69928518T2 (de) 2006-03-30
CN1294835A (zh) 2001-05-09
EP1811825A1 (de) 2007-07-25

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