JPH0348232U - - Google Patents

Info

Publication number
JPH0348232U
JPH0348232U JP1989108936U JP10893689U JPH0348232U JP H0348232 U JPH0348232 U JP H0348232U JP 1989108936 U JP1989108936 U JP 1989108936U JP 10893689 U JP10893689 U JP 10893689U JP H0348232 U JPH0348232 U JP H0348232U
Authority
JP
Japan
Prior art keywords
hybrid
board
wire
semiconductor chips
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1989108936U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989108936U priority Critical patent/JPH0348232U/ja
Publication of JPH0348232U publication Critical patent/JPH0348232U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【図面の簡単な説明】
第１図は本考案の混成ＩＣの一実施例の断面図
、第２図は本考案の混成ＩＣの他の実施例の断面
図、第３図は従来の混成ＩＣの断面図、第４図は
混成ＩＣの回路構成の例を示す回路図である。 符号の説明、１……ＬＥＤ、２……トランジス
タ、３……抵抗、４……ワイヤ、５……論理回路
、６……セラミツクス配線基板、７……ＬＥＤア
レイチツプ、８……ドライバＩＣチツプ、９……
抵抗、１０，１０ａ……基板上配線、１１……配
線ワイヤ、１２……抵抗ワイヤ、１２ａ，１２ｂ
……抵抗ワイヤ。

Claims (1)

  1. 【実用新案登録請求の範囲】 基板上で半導体チツプ間、あるいは半導体チツ
    プと基板上配線の間をワイヤで接続した混成ＩＣ
    において、 前記ワイヤが所定の抵抗値を有する抵抗線によ
    つて構成されることを特徴とする混成ＩＣ。
JP1989108936U 1989-09-18 1989-09-18 Pending JPH0348232U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989108936U JPH0348232U (ja) 1989-09-18 1989-09-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989108936U JPH0348232U (ja) 1989-09-18 1989-09-18

Publications (1)

Publication Number Publication Date
JPH0348232U true JPH0348232U (ja) 1991-05-08

Family

ID=31657545

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989108936U Pending JPH0348232U (ja) 1989-09-18 1989-09-18

Country Status (1)

Country Link
JP (1) JPH0348232U (ja)

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