JPS6183046U - - Google Patents

Info

Publication number
JPS6183046U
JPS6183046U JP1984169644U JP16964484U JPS6183046U JP S6183046 U JPS6183046 U JP S6183046U JP 1984169644 U JP1984169644 U JP 1984169644U JP 16964484 U JP16964484 U JP 16964484U JP S6183046 U JPS6183046 U JP S6183046U
Authority
JP
Japan
Prior art keywords
semiconductor element
groove
main part
resin material
thin metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984169644U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984169644U priority Critical patent/JPS6183046U/ja
Publication of JPS6183046U publication Critical patent/JPS6183046U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/127—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed characterised by arrangements for sealing or adhesion
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】
第１図は本案の一実施例を示す側断面図、第２
図は第１図の要部拡大図、第３図は従来例の側断
面図、第４図は第３図の要部拡大図である。 図中、１は放熱板、２は溝部、２ａは突出部、
３は半導体素子、４はリード、５は金属細線、６
は樹脂材である。

Claims (1)

    【実用新案登録請求の範囲】
  1. 上面に形の溝部を有する放熱板に半導体素子
    を固定すると共に、それの電極とリードとを金属
    細線にて接続し、かつ半導体素子を含む主要部分
    を樹脂材にてモールド被覆したものにおいて、上
    記溝部の底面に山形の突出部を形成したことを特
    徴とする半導体装置。
JP1984169644U 1984-11-07 1984-11-07 Pending JPS6183046U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984169644U JPS6183046U (ja) 1984-11-07 1984-11-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984169644U JPS6183046U (ja) 1984-11-07 1984-11-07

Publications (1)

Publication Number Publication Date
JPS6183046U true JPS6183046U (ja) 1986-06-02

Family

ID=30727363

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984169644U Pending JPS6183046U (ja) 1984-11-07 1984-11-07

Country Status (1)

Country Link
JP (1) JPS6183046U (ja)

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