JPS6232541U - - Google Patents

Info

Publication number
JPS6232541U
JPS6232541U JP1985124061U JP12406185U JPS6232541U JP S6232541 U JPS6232541 U JP S6232541U JP 1985124061 U JP1985124061 U JP 1985124061U JP 12406185 U JP12406185 U JP 12406185U JP S6232541 U JPS6232541 U JP S6232541U
Authority
JP
Japan
Prior art keywords
protective film
covered
semiconductor device
bonding pad
pad portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985124061U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985124061U priority Critical patent/JPS6232541U/ja
Publication of JPS6232541U publication Critical patent/JPS6232541U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/981—Auxiliary members, e.g. spacers
    • H10W72/983—Reinforcing structures, e.g. collars

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図は本考案の一実施例の半導体装置の断面
図、第２図は従来の半導体装置の断面図である。 １１……サブストレート、１２……エピタキシ
ヤル層、１３……導通領域、１４……酸化膜、１
４ａ，１４ｂ……窓、１５……配線、１５ａ……
ボンデイングパツド、１６……保護膜、１７……
分離領域、１８……金線、１８ａ……ボール。

Claims (1)

  1. 【実用新案登録請求の範囲】 配線のボンデイングパツド部分を除く上面の他
    の部分を保護膜で覆い、該ボンデイングパツド部
    分にワイヤをボンデイングした半導体装置におい
    て、 上記ボンデイングパツド部分と上記配線におけ
    る上記保護膜で覆われた部分との間を、半導体層
    内に形成した導通領域により接続してなることを
    特徴とする半導体装置。
JP1985124061U 1985-08-14 1985-08-14 Pending JPS6232541U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985124061U JPS6232541U (ja) 1985-08-14 1985-08-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985124061U JPS6232541U (ja) 1985-08-14 1985-08-14

Publications (1)

Publication Number Publication Date
JPS6232541U true JPS6232541U (ja) 1987-02-26

Family

ID=31015732

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985124061U Pending JPS6232541U (ja) 1985-08-14 1985-08-14

Country Status (1)

Country Link
JP (1) JPS6232541U (ja)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61147553A (ja) * 1984-12-21 1986-07-05 Toshiba Corp 半導体装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61147553A (ja) * 1984-12-21 1986-07-05 Toshiba Corp 半導体装置

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